Metal oxide semiconductor transistor with self-aligned channel implant

ABSTRACT

A transistor ( 50 ) comprising a gate conductor ( 68 ) and a gate insulator ( 66 ) separating the gate conductor from a semiconductor material ( 64 ) having a first conductivity type. The transistor further comprises a drain region ( 72   2 ) having the first conductivity type. The transistor further comprises an angular implanted region ( 70 ) having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge ( 70   a ) underlying the gate conductor, and the transistor includes a source region ( 72   1 ) formed at least in part within the angular implanted region. Finally, a transistor channel ( 74 ) is defined between an edge ( 72   a   1 ) of the source region proximate the gate conductor and the angular implanted region edge ( 70   a ) underlying the gate conductor.

CROSS-REFERENCES TO RELATED APPLICATIONS

[0001] Not Applicable.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] Not Applicable.

BACKGROUND OF THE INVENTION

[0003] The present embodiments relate to metal oxide semiconductor(“MOS”) transistors and are more particularly directed to such atransistor with a self-aligned channel implant.

[0004] Electronic circuit design is often critically affected by thedesign of individual transistors used within a circuit. As a result,transistor design has developed for years and continues to be an area ofextensive research for various issues, including uniformity of operationbetween multiple transistors constructed according to a same design aswell as device reliability. In this regard, MOS field effect transistor(“MOSFET”) design typically specifies parameters and methods relating tothe formation of various components relative to a semiconductorsubstrate, including the creation of doped regions within the substrate.Consequently, these parameters and methods affect aspects such asoperational uniformity and reliability.

[0005] One aspect of a MOSFET where the above considerations isimplicated is in the formation of the transistor channel, which as knownin the art is the area in which a current may be induced to flow betweenthe source and drain of the transistor. The locations of the regionsthat define the channel, as well as the length of the channel, mayaffect operational uniformity and reliability as well as other aspectsrelating to the transistor. Channel length may be an issue in varioustransistors, including one type of known MOSFET referred to in the artas a drain extended MOS (“DEMOS”) transistor. A DEMOS transistor isdetailed later but is also introduced here by way of background. A DEMOStransistor is named due to having a drain region formed from tworegions, a first region having a doping level comparable to that of thetransistor source and a second region having a reduced doping level andwhich extends under the transistor gate. DEMOS transistors are used invarious circuits, where one instance is a circuit that has differentoperating voltages such as where a first voltage is used at theinput/output level while a second and lower voltage is used for theoperational core of the circuit. In these cases, transistors suitablefor use at the higher input/output voltages are required, and one typeof such a transistor is the DEMOS transistor. DEMOS transistors also maybe used in applications where the voltage on the drain exceeds thenormal voltage rating of the gate oxide.

[0006] Given the preceding, it has been observed by the presentinventors that for the DEMOS transistor, and possibly for other MOSFETs,some approaches in the art form regions that define the transistorchannel prior to the formation of the transistor gate. For example, forthe DEMOS transistor the channel may be defined relative to aninsulating region which generally defines the transistor active region.However, often such designs leave room for variation in the channellength as well as the actual formation of the channel, where bothaspects may be affected by the later-formed transistor gate.Consequently, these variations may affect device uniformity andreliability. The preferred embodiments seek to improve upon thesedrawbacks, as further explored below.

BRIEF SUMMARY OF THE INVENTION

[0007] In the preferred embodiment, there is a transistor. Thetransistor comprises a gate conductor and a gate insulator separatingthe gate conductor from a semiconductor material having a firstconductivity type. The transistor further comprises a drain regionhaving the first conductivity type. The transistor further comprises anangular implanted region having a second conductivity type complementaryof the first conductivity type and having an angular implanted regionedge underlying the gate conductor, and the transistor includes a sourceregion formed within the angular implanted region. Finally, a transistorchannel is defined between an edge of the source region proximate thegate conductor and the angular implanted region edge underlying the gateconductor. Other aspects are also disclosed and claimed.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0008]FIG. 1a illustrates a cross-sectional view of a prior art DEMOStransistor 10.

[0009]FIG. 1b illustrates a cross-sectional view of the prior art DEMOStransistor 10 from FIG. 1a after some preliminary construction steps.

[0010]FIG. 1c illustrates a cross-sectional view of the prior art DEMOStransistor 10 from FIG. 1b after additional construction steps.

[0011]FIG. 2a illustrates a cross-sectional view of a preferredembodiment DEMOS transistor after some preliminary construction steps.

[0012]FIG. 2b illustrates a cross-sectional view of the inventive DEMOStransistor from FIG. 2a after additional construction steps.

[0013]FIG. 2c illustrates a cross-sectional view of the inventive DEMOStransistor from FIG. 2b after additional construction steps.

[0014]FIG. 2d illustrates a cross-sectional view of the inventive DEMOStransistor from FIG. 2c after additional construction steps.

[0015]FIG. 3 illustrates a cross-sectional view of an alternativepreferred embodiment transistor.

DETAILED DESCRIPTION OF THE INVENTION

[0016] By way of additional introduction to the prior art beyond thatdiscussed in the earlier Background Of The Invention section of thisdocument, FIG. 1a illustrates a cross-sectional view of a prior artDEMOS transistor 10. To present a more thorough appreciation of DEMOStransistor 10, the following discussion first introduces its variouscomponents while a later discussion elaborates on the method and orderin which various of those components are formed.

[0017] Transistor 10 is formed relative to a substrate 20 which, in theexample of FIG. 1a, is formed from a p-type semiconductor material. Ashallow trench isolation (“STI”) region 22 is formed in substrate 20 andmay be various insulating materials such as silicon oxide or siliconnitride. Two well regions 24 and 26 of opposite conductivity types areformed in substrate 20 and with an interface 28 between the two. In theexample of FIG. 1a well 24 is an n-type well and well 26 is a p-typewell and, thus, are labeled generally with an N and P, respectively. Agate dielectric 30 is formed over substrate 20, and a gate conductor 32is formed over gate dielectric 30 and extends partially over STI region22. For the sake of reference, gate conductor 32 is also shown by aschematic indication in FIG. 1a with the identifier “G₁.” A lightlydoped region 31 is formed self-aligned to edge 32 a of gate conductor32, such as by implanting n-type dopants in the area of edge 32 a andwhere those dopants diffuse slightly under gate conductor 32 and gatedielectric 30. Thereafter, sidewall insulators 33 ₁ and 33 ₂ are formedalong edges 32 a and 32 b, respectively of gate conductor 32. Two dopedregions 34 ₁ and 34 ₂ are formed within substrate 20 and areself-aligned to sidewall insulators 33 ₁ and 33 ₂ (and, hence, also togate conductor 32). In the present example, regions 34 ₁ and 34 ₂ aren-type regions with relatively high doping concentrations (e.g.,relative to n-well 24) and are, therefore, labeled in FIG. 1a with an N+designation. Generally, region 34 ₁ combines with the previously-formedlightly doped region 31 and the combination is considered to provide thesource of transistor 10 and is schematically labeled “S₁”, and region 34₂ is considered to provide in part the drain of transistor 10 and isschematically labeled “D₁.” Note that region 34 ₂ as an n-type regionfunctions only as part of the drain of transistor 10 in that thelike-conductivity type n-well 24 effectively extends the drain regionunder gate conductor 32. Accordingly, a transistor channel 36 is definedunder gate conductor 32 and extending between the left edge of n-well 24and the right edge of the source region S₁ which includes regions 34 ₁and 31. Lastly, note that other components may be added to transistor 10(e.g., body contact, sidewall insulators, and so forth), although suchcomponents are not shown to simplify the Figure and since they areunnecessary to further appreciate the preferred embodiments discussedlater.

[0018] Having described the various parts of transistor 10 of FIG. 1a, afurther appreciation of some of those parts is facilitated byunderstanding certain steps of the formation of transistor 10 as is nowexplored with reference to FIG. 1b. Specifically, FIG. 1b illustrates across-sectional view of the prior art DEMOS transistor 10 from FIG. 1aafter some preliminary construction steps. In FIG. 1b, STI region 22 isformed first in substrate 20, and it typically defines an adjacent areagenerally referred to as the active area, that is, the area in which thetransistor source/drain regions will be formed. STI region 22 typicallyis formed by first forming a pit or void within the upper surface ofsubstrate 20 and then filling the pit with an insulator and planarizingthe insulator to leave the remaining insulator portion shown in FIG. 1bas STI region 22. After STI region 22 is formed, well regions 24 and 26are formed in substrate 20, typically one immediately after the other,and using dopants of opposite conductivity types. Each well 24 and 26typically is formed by masking the surface of substrate 20 and thenimplanting appropriate dopants through any open area of the mask; thus,in the example of FIG. 1a, well 24 is formed using n-type dopants whilewell 26 is formed using p-type dopants. Typically wells 24 and 26 areformed with a goal that they abut one another and thereby form thegenerally vertical interface 28 between the two wells. However, notethat the alignment of wells 24 and 26 is established purely by aphotolithographic process relative to STI region 22. In other words,typically STI region 22 has some type of marker on it that isphotographically recognized by the stepper machine that fabricatestransistor 10, and in response to this marker the stepper in combinationwith the masks used to form wells 24 and 26 thereby determine thephysical distance offset of each well boundary relative to STI region22. As a result of variations in this photolithographic alignment, notethat wells 24 and 26 may not align in the intended manner.

[0019]FIG. 1c illustrates a cross-sectional view of the prior art DEMOStransistor 10 from FIG. 1b after additional construction steps. Gatedielectric 30 is formed over substrate 20, and it may be an oxide, athermally grown silicon dioxide, a nitride, an oxynitride, or acombination of these or other insulators. Gate conductor 32 is formedover gate dielectric 30 and is patterned to extend partially over STIregion 22, such as by forming a layer of conductive material which ispatterned and etched to form gate conductor 32. Further, gate conductor32 is typically formed from polysilicon, although other materials may beused. In any event, because gate conductor 32 is formed after wells 24and 26, the alignment of gate conductor 32 with respect to those wells,which by way of example may be appreciated from either edge 32 a or 32 bof gate conductor 32 relative to interface 28, is also subject tovariations of the photolithographic process that is used to form gateconductor 32. For example, if in FIG. 1c gate conductor 32 were shiftedto the left, this would increase the distance between edge 32 a andinterface 28 while decreasing the distance between edge 32 b andinterface 28. As another example, if in FIG. 1c gate conductor 32 wereshifted to the right, this would decrease the distance between edge 32 aand interface 28 while increasing the distance between edge 32 b andinterface 28. After gate conductor 32 is formed, lightly doped region 31is formed self-aligned to edge 32 a of gate conductor 32 by implantingn-type dopants in the area of edge 32 a. Typically, the n-type dopantsare at a lesser concentration than those used for n-type regions 34 ₁and 34 ₂ (see FIG. 1a).

[0020] Concluding the details of the formation of transistor 10,attention may be returned to FIG. 1a given the previous stepsillustrated from FIG. 1c. Once gate conductor 32 is formed, dopedregions 34 ₁ and 34 ₂ are formed within substrate 20, typically byimplanting the appropriate (e.g., n-type) dopants into wells 24 and 26and then following with an annealing step. With respect to source region34 ₁, note that the portion of it adjacent channel 36 is self-alignedwith respect to edge 32 a of gate conductor 32, meaning edge 32 acreates a physical mask and, thus, a physical reference point relativeto where the edge of region 34 ₁ is formed in response to the dopantimplant. In addition, the subsequent anneal may cause some lateralencroachment of the dopants of region 34 ₁ so that they actually extendunder gate conductor 32 as shown. In any event, therefore, the edge ofsource region 34 ₁ which defines one end of channel 36 is defined inresponse to a physical component self-alignment rather than aphotolithographic alignment. The other edge of source region 34 ₁ (notshown, but to the left in the Figure), however, may be defined byphotolithographic alignment, such as in response to a mask, or inresponse to another STI or field oxide insulator. With respect to drainregion 34 ₂, its edge proximate STI region 22 is self-aligned with theedge of STI region 22 while its other edge (not shown, but to the rightin the Figure) may be defined by photolithographic alignment, such as inresponse to a mask, or in response to another STI or field oxideinsulator.

[0021] The present inventors have observed various drawbacks associatedwith prior art transistor 10, and those drawbacks should be more readilyappreciated in view of the preceding discussion of FIGS. 1a through 1 c.Specifically, as introduced above, the prior art transistor is subjectto various misalignments, and any of these misalignments may undesirablyaffect the predictability of the device's operation and its uniformityrelative to other like transistors formed at the same time with respectto substrate 20. Indeed, there are many different possiblemisalignments. For instance, recalling that p-well 26 is aligned by aphotolithographic process, then it may be formed such that its rightedge as shown in FIG. 1a is shifted to the left, thereby presenting agap between it and the left edge of n-well 24. Similarly, since n-well24 is also aligned by a photolithographic process, then it may be formedsuch that its left edge as shown in FIG. 1a is shifted to the right,presenting a gap between it and the right edge of p-well 26. In eithercase, the goal of a common interface 28 is not achieved, and this mayaffect the behavior of operation along channel 36. As a result, althoughthe edge of source 34 ₁ under gate conductor 32 is self-aligned and,thus, relatively well-controlled, a shift in the edge of either p-well26 or n-well 24 under gate conductor 32 may affect the length of channel36 and, therefore, may undesirably affect the predicted operation of thedevice. As a final example, wells 24 and 26 may overlie one another moreextensively than intended along interface 28 such that the dopants fromthe second-formed of the two wells are more heavily infused into thefirst-formed of the two wells. From the preceding, it may be appreciatedthat the channel length is susceptible to a compound alignment sincegate conductor 32 and the well boundaries are all photolithographicallyaligned. Hence, a minimum channel length, which is often highly desired,is limited by photolithographic process variations.

[0022]FIG. 2a illustrates a cross-sectional view of a preferredembodiment DEMOS transistor 50 after some preliminary constructionsteps. Transistor 50 is constructed relative to a substrate 60 which, inthe present example and the preferred embodiment, is a p-typesemiconductor substrate and is preferably part of an integrated circuit.An STI region 62 is formed first in substrate 60, and like the prior artit defines an adjacent area generally referred to as the active area,that is, the area in which the transistor source/drain regions will beformed. However, as further appreciated below, the alignment of variousregions in the preferred embodiment are not relative to STI region 62 asthey are in the prior art. STI region 62 is formed by first forming apit or void within the upper surface of substrate 60 and then fillingthe pit with an insulator and planarizing the insulator to leave theremaining insulator portion shown in FIG. 2a as STI region 62. After STIregion 62 is formed, a well 64 is formed in substrate 60, and in thepreferred embodiment well 64 is formed using n-type dopants to therebycreate an n-well 64. Note that n-well 64 extends laterally across theentire span of FIG. 2a and, thus, it is not tightly constrained relativeto STI region 22; however, its outer edges (not shown) may byphotographically aligned with respect to STI region 22, but those edgesare of lesser consequence because they do not lie proximate the gateconductor which is formed later. Alternatively these outer areas may beself-aligned relative to other STI or field oxide regions. In any event,n-well 64 preferably is formed by masking the surface of substrate 60and then implanting dopants through any open area of the mask.

[0023]FIG. 2b illustrates a cross-sectional view of DEMOS transistor 50from FIG. 2a after additional construction steps. A gate dielectric 66is formed over substrate 60, and it may be an oxide, a thermally grownsilicon dioxide, a nitride, an oxynitride, or a combination of these orother insulators. A gate conductor 68 is formed over gate dielectric 66and is patterned to extend partially over STI region 62, such as byforming a layer of conductive material which is patterned and etched toform gate conductor 68. Further, gate conductor 68 may be formed frompolysilicon, although other materials may be used. After gate conductor68 is formed, an angular implant is performed in the area shown in FIG.2b to the left of gate conductor 68 and for the purpose of forming ap-well 70, that is, to form a well of opposite conductivity typerelative to well 64 (which is n-type). Further in this regard, note thatsuch an angular implant has been used in the art of formation of othersemiconductor devices, but typically it is used to form a second regionof a same conductivity type as the first region within which the secondregion is formed (e.g., a p-region in a p-well or an n-region in ann-well). In such devices, the angular implant is sometimes referred toas a halo implant or a pocket implant. In any event, due to the angularnature of the implant, part of p-well 70 extends laterally underneathgate conductor 68 to a greater extent than if a standard verticalimplant were used, and in the preferred embodiment a subsequent annealis performed which may cause the p-type dopants to encroach laterallyeven more so under gate conductor 68. As is important for reasonsdetailed later, note that the formation of p-well 70 defines an edge 70a underneath gate conductor 68, and edge 70 a is self-aligned to edge 68a of gate conductor 68. In other words, the location of edge 70 a occursdue to the masking effect of a physical device structure, namely, gateconductor 68 rather than from a photolithographically imposed edge suchas from a photolithographic mask.

[0024]FIG. 2c illustrates a cross-sectional view of DEMOS transistor 50from FIG. 2b after an additional construction step. An n-type region 71is formed preferably using a standard implant followed by an annealingstep, with region 71 being formed in p-well 70 and preferably using arelatively light doping concentration as compared to higher-doped n-typeregions formed below in connection with FIG. 2d. In one embodiment,region 71 may be formed using the same mask as is used to form p-well70, but using a lower energy than used for p-well 70 and also using avertical implant, whereby the combination of these factors yields adepth of penetration of the dopants that is less than that of well 70 asshown. Additionally, for the formation of region 71, there may not be aneed for a separate mask for that lightly doped region since, likep-well 70, region 71 also self-aligns to edge 68 a of gate conductor 68.As an alternative embodiment, however, a separate mask may be used.Further, typically the annealing step used in the formation of region 71causes it to diffuse slightly under gate conductor 68 and gatedielectric 66. As further detailed below, region 71 forms part of thesource for transistor 50, whereas n-well 64 acts in part as the drain oftransistor 50. As a result, a transistor channel 74 is defined undergate conductor 68 and extending between the interface between edge 70 aand n-well 64 and the right edge 71 a of region 71.

[0025]FIG. 2d illustrates a cross-sectional view of DEMOS transistor 50from FIG. 2c after additional construction steps. Sidewall insulators 76₁ and 76 ₂ are formed along edges 68 a and 68 b, respectively, ofconductor 68, such as by forming an insulator layer over the entirestructure and etching it appropriately. Thereafter, two doped regions 78₁ and 78 ₂ are formed at the same time and preferably using a standardimplant followed by an annealing step, with region 78 ₁ being formed inp-well 70 and acting in combination with region 71 as the source S₂while region 78 ₂ is formed in n-well 64 and acts in part as the drainD₂. In the preferred embodiment, regions 78 ₁ and 78 ₂ are n-typeregions with relatively high doping concentrations (e.g., relative ton-well 64 and region 71) and are, therefore, labeled in FIG. 2d with anN+ designation. Region 78 ₁ has one edge 78 a ₁ proximate and preferablyslightly under sidewall insulator 76 ₁, while its other edge extendsaway from gate conductor 68 (and is not shown, but would be to the leftin FIG. 2d). Region 78 ₂ has one edge 78 a ₂ proximate and abutting STIregion 62, while its other edge extends away from gate conductor 68 andSTI region 62 (and is not shown, but would be to the right in FIG. 2d).Thus, in operation, when a large drain voltage is applied relative togate conductor 68, then considerable voltage may be dropped across STIregion 62 between gate conductor 68 and region 78 ₂, thereby avoidingdamage to gate dielectric 66. Further, n-type region 78 ₂ functions onlyas part of the drain of transistor 50 in that the like conductivity typen-well 64 effectively extends the drain region under gate conductor 68.Accordingly, transistor channel 74 is defined under gate conductor 68and extending between the interface between edge 70 a and n-well 64 andthe right edge 71 a of lightly doped region 71.

[0026] Given the preceding, various observations may be made relative tothe preferred embodiment such as with reference to FIG. 2d. As a firstobservation and with respect to regions 71 and 78 ₁, note that each hasan edge that is self-aligned with respect to gate conductor 68. Withrespect to region 71, its edge 71 a, which is adjacent channel 74, isself-aligned with respect to edge 68 a of gate conductor 68, meaningedge 68 a creates a physical mask and, thus, a physical reference pointrelative to where edge of region 71 a is formed in response to thedopant implant. With respect to region 78 ₁, its edge 78 a ₁ isself-aligned with respect to sidewall insulator 76 ₁. Here, sidewallinsulator 76 ₁ creates the physical reference point relative to whereedge 78 a ₁ is formed in response to the dopant implant. Lastly, becausesidewall insulator 76 ₁ is fixed to gate conductor 68, then edge 78 a ₁is also therefore self-aligned relative to gate conductor 68. As asecond observation, therefore, note that the lateral length of channel74 is defined only by self-aligned features. More particularly, the leftedge 74 a of channel 74 is defined by the self-aligned right edge 71 aof region 71, and the right edge 74 b of channel 74 is defined by theself-aligned right edge 70 a of p-well 70. Accordingly, both edges 74 aand 74 b of channel 74 are self-aligned, and in the preferred embodimentthey are self-aligned relative to edge 68 a of gate conductor 68. As aresult, the length of channel 74 is more predictable as compared to adevice, such as transistor 10 of the prior art, wherein at least one orboth edges of the channel are photolithographically defined as opposedto self-aligned. This improvement in channel length predictability givesrise to greater uniformity for various transistors formed in a mutualsubstrate using the same design as transistor 50, and when implementedas a DEMOS transistor there is the added advantage of improved devicereliability. As still another benefit, the length of channel 74 isdetermined primarily by the angular implant used to form p-well 70 and,thus, by controlling the angular implant a considerably small channelmay be achieved, and such a small channel may be highly desirable invarious instances.

[0027] The preceding has demonstrated various benefits of the preferredembodiment, many of which arise in connection with the formation ofp-well 70 using an angular implant. Further in this regard, note thatvarious alternatives are also contemplated within the present inventiveteachings as relating to that angular implant. As a first embodiment forthe p-well 70 formation step, note that transistor 50 may be constructedrelative to substrate 60 at the same time that other devices are beingformed relative to that same substrate. Further, some of those otherdevices may use an angular implant for other reasons, such as forming asecond region within a previously-formed region, where both regions havethe same conductivity type as mentioned earlier. Given this possibility,in one approach the formation of p-well 70 may occur during the samestep of using the angular implant for other reasons, that is, the sameenergy level and dopant concentration used for the other devices may beused to form p-well 70. In such an approach, no additional fabricationsteps are required to construct transistor 50 that were not alreadyrequired to construct other devices relative to substrate 60. As asecond embodiment for the p-well 70 formation, however, a separateangular implant, with a different energy and/or dopant concentration,may be used solely to create p-well 70 (and any other comparable wellsfor other transistors like transistor 50 then being formed in substrate60). This latter approach increases the number of fabrication steps, butit also gives added flexibility in the formation of p-well 70 andlikewise in the design flexibility for channel 74.

[0028] Still another benefit of the preferred embodiment arises whentransistor 50 is implemented as an input/output transistor on a circuithaving different transistor characteristics for its input/outputtransistors versus its core transistors, as is commonly the case incontemporary circuits where, by way of example, the core transistors mayoperate at a lesser voltage than the input/output transistors such asdiscussed in the Background Of The Invention section of this document.In such an embodiment, the core transistors typically includesource/drain regions that use two implants, a first for forming an LDDportion extending under the transistor gate, and a second implantforming the remainder of the source/drain region extending away from thetransistor channel. In connection with transistor 50 and as introducedabove, the same implant step used to form the n-type LDD portions forthe core transistors also may be used to form n-type LDD region 71 oftransistor 50 in the input/output circuit. Thus, there is no need for anadditional and different implant step to form n-type LDD region 71beyond that already provided for in constructing the core transistors.In addition, no LDD region need be formed in connection with drain D₂ oftransistor 50, because the effective lighter doping of drain D₂ isachieved in connection with n-well 64, and that well may be created atthe same time as are other n-wells that will be required to constructp-type devices in a CMOS architecture. As a result, this elimination ofadditional patterning and related steps may produce a valuable costsavings for a process flow used for dual voltage integrated circuits.

[0029] Yet another alternative in the preferred embodiment is shown inFIG. 3, which illustrates a cross-sectional view of an alternativepreferred embodiment transistor designated generally at 80. Transistor80 shares many attributes that are comparable to transistor 50 describedabove and, thus, these attributes are not discussed in significantdetail. Looking briefly to these comparable attributes, transistor 80 isconstructed relative to a substrate 90, which preferably is a p-typesemiconductor substrate. An n-well 92 is formed in substrate 90, and agate dielectric 94 is formed over substrate 90 and, hence, over n-well92. Next, a gate conductor 96 is formed over gate dielectric 94,preferably from polysilicon or other suitable materials. After gateconductor 96 is formed, an angular implant is performed in the areashown in FIG. 3 to the left of gate conductor 96 and for the purpose offorming a p-well 98, thereby forming a well of opposite conductivitytype relative to well 92 (which is n-type). Due to the angular nature ofthe implant, part of p-well 98 extends laterally underneath gateconductor 96 to a greater extent than if a standard vertical implantwere used, and in the preferred embodiment a subsequent anneal isperformed which may cause the p-type dopants to encroach laterally evenmore so under gate conductor 96. The formation of p-well 98 defines anedge 98 a underneath gate conductor 96, and edge 98 a is self-aligned toedge 96 a of gate conductor 96.

[0030] After gate conductor 96 and p-well 98 are formed, a lightly dopedregion 100 ₁ is formed self-aligned to edge 96 a of gate conductor 96and within p-well 98. Preferably, region 100 ₁ is formed using astandard vertical implant with a relatively light doping concentrationand followed by an annealing step which causes both regions to diffuseslightly under gate conductor 96 and gate dielectric 94. In oneembodiment, region 100 ₁ may be formed using the same mask as is used toform p-well 98, but using a lower energy and vertical implant so thatthe depth of penetration of the dopants is less than that of well 98 asshown. Additionally, for the formation of region 100 ₁, there may not bea need for a separate mask for that lightly doped region since, likep-well 98, region 100 ₁ also self-aligns to edge 96 a of gate conductor96. As an alternative embodiment, however, a separate mask may be used.In any event, after the formation of region 100 ₁, sidewall insulators102 ₁ and 102 ₂ are formed along edges 96 a and 96 b, respectively, ofgate conductor 96. Following that step, two symmetric doped regions 104₁ and 104 ₂ are formed at the same time and preferably using a standardimplant followed by an annealing step, with region 104 ₁ being formed inp-well 98 and acting in combination with region 100 ₁ as the source S₃while region 104 ₂ is formed in n-well 92 and acts in part as the drainD₃. Preferably, regions 104 ₁ and 104 ₂ are n-type regions withrelatively high doping concentrations (e.g., relative to n-well 92 andregions 100 ₁ and 100 ₂) and are, therefore, labeled in FIG. 3 with anN+ designation.

[0031] Having detailed the various components of transistor 80, notethat its source S₃, as comprising region 104 ₁ and region 100 ₁, isself-aligned with respect to gate conductor 96. Specifically, region 100₁ is adjacent a channel 106 and is self-aligned with respect to edge 96a of gate conductor 96, while region 104 ₁ is self-aligned with respectto sidewall insulator 102 ₁ and, hence, also with respect to gateconductor 96. Moreover, edge 98 a of p-well 98 is self-aligned relativeto gate conductor 96 for the same reasons as discussed above relative top-well 70 of transistor 50. Thus, the length of channel 106 iswell-controlled because both of its lateral boundaries, shown verticallyin FIG. 3, are self-aligned boundaries. As a result, the length ofchannel 106 is more predictable as compared to a prior art device suchas transistor 10 of the prior art and, hence, device reliability andoperability in the preferred embodiment are improved.

[0032] From the above, it may be appreciated that the above embodimentsprovide an improved transistor with a self-aligned channel implant andgives rise to numerous improvements over the prior art. Further, whilevarious alternatives have been provided above, others are contemplatedwithin the inventive scope. For example, other components may be addedto transistor 50 in addition to those shown in FIG. 2d or to transistor80 shown in FIG. 3. As another example, while one preferred transistoris illustrated as a particular configuration of a DEMOS transistor,other DEMOS transistors or indeed, transistors other than DEMOStransistors, also may benefit from the present inventive teachings. Asyet another example, when the preferred embodiment is implemented as aDEMOS transistor, it may connected in various circuit configurations.For example, the preferred embodiment may prove quite useful forinput/output connections, such as in an open drain/collectorconfiguration. In one instance of such a configuration, the drain oftransistor 50 may be physically isolated and connected directly to anintegrated circuit bond pad. As still another example, while thepreferred embodiment has been illustrated as an n-channel transistor,the present teachings may be used to form a comparable p-channeltransistor by complementing various of the material conductivity typesdescribed above. Still further, additional alterations may beascertained by one skilled in the art. Consequently, while the presentembodiments have been described in detail, various substitutions,modifications or alterations could be made to the descriptions set forthabove without departing from the inventive scope which is defined by thefollowing claims.

1. A transistor, comprising: a gate conductor; a gate insulatorseparating the gate conductor from a semiconductor material having afirst conductivity type; a drain region having the first conductivitytype; an angular implanted region having a second conductivity typecomplementary of the first conductivity type and having an angularimplanted region edge underlying the gate conductor; a source regionformed within the angular implanted region; and a transistor channeldefined between an edge of the source region proximate the gateconductor and the angular implanted region edge underlying the gateconductor:
 2. The transistor of claim 1 wherein the edge of the sourceregion proximate the gate conductor is self-aligned with respect to thegate conductor.
 3. The transistor of claim 2 wherein the angularimplanted region edge underlying the gate conductor is self-aligned withrespect to the gate conductor.
 4. The transistor of claim 3 wherein thesemiconductor material having a first conductivity type comprises asemiconductor material having an n-type.
 5. The transistor of claim 4:and further comprising a p-type semiconductor substrate; and wherein thesemiconductor material comprises an n-well formed in the p-typesemiconductor substrate.
 6. The transistor of claim 5 and furthercomprising: a gate insulator separating at least a portion of the gateconductor from the semiconductor material; and an insulating regionproximate one edge of the gate conductor; and wherein the drain regionhas a first edge abutting the insulating region and a second edgeextending away from the insulating region and the gate conductor.
 7. Thetransistor of claim 6 wherein the drain region has a higher dopantconcentration than the semiconductor material.
 8. The transistor ofclaim 7 wherein the source region has the first conductivity type. 9.The transistor of claim 1 wherein the angular implanted region edgeunderlying the gate conductor is self-aligned with respect to the gateconductor.
 10. The transistor of claim 1 wherein the semiconductormaterial having a first conductivity type comprises a semiconductormaterial having an n-type.
 11. The transistor of claim 1: and furthercomprising a p-type semiconductor substrate; and wherein thesemiconductor material comprises an n-well formed in the p-typesemiconductor substrate.
 12. The transistor of claim 1 and furthercomprising: a gate insulator separating at least a portion of the gateconductor from the semiconductor material; and an insulating regionproximate one edge of the gate conductor; and wherein the drain regionhas a first edge abutting the insulating region and a second edgeextending away from the insulating region and the gate conductor. 13.The transistor of claim 1 wherein the drain region has a higher dopantconcentration than the semiconductor material.
 14. The transistor ofclaim 1 wherein the source region has the first conductivity type.
 15. Amethod of forming an integrated circuit, comprising the steps of:forming a gate insulator; forming a gate conductor relative to the gateinsulator such that the gate insulator separates the gate conductor froma semiconductor material having a first conductivity type; forming adrain region having the first conductivity type; performing an angularimplant to form an angular implanted region having a second conductivitytype complementary of the first conductivity type and having an angularimplanted region edge underlying the gate conductor; forming a sourceregion formed within the angular implanted region; and wherein the stepsof performing an angular implant and forming a source region define atransistor channel between an edge of the source region proximate thegate conductor and the angular implanted region edge underlying the gateconductor.
 16. The method of claim 15: wherein the gate insulator, thegate conductor, the source region, the drain region, and the angularimplanted region form a first transistor; and further comprising forminga second transistor comprising the step of using the angular implant toform at least one region of the second transistor into apreviously-formed region of the second transistor.
 17. The method ofclaim 16 wherein the at least one region has a conductivity type whichis the same as a conductivity type of the previously-formed region. 18.The method of claim 15 wherein the edge of the source region proximatethe gate conductor is self-aligned with respect to the gate conductor.19. The method of claim 18 wherein the angular implanted region edgeunderlying the gate conductor is self-aligned with respect to the gateconductor.
 20. The method of claim 19 wherein the semiconductor materialhaving a first conductivity type comprises a semiconductor materialhaving an n-type.
 21. The method of claim 20 wherein the semiconductormaterial comprises an n-well formed in a p-type semiconductor substrate.22. The method of claim 21 and further comprising: forming a gateinsulator separating at least a portion of the gate conductor from thesemiconductor material; and forming an insulating region proximate oneedge of the gate conductor; and wherein the drain region has a firstedge abutting the insulating region and a second edge extending awayfrom the insulating region and the gate conductor.
 23. The method ofclaim 22 wherein the drain region has a higher dopant concentration thanthe semiconductor material.